The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this disclosure and are not admitted to be prior art by inclusion in this section.
To accommodate user's ever-increasing expectations for computing performance, many memories technologies are moving to three-dimensional (3D) geometries to increase memory density. By stacking layers of memory cells, these 3D geometries and memory structures enable the storage of more data in comparison to traditional planar or two-dimensional (2D) memory structures. The stacked layers of memory cells, however, often prevent heat generated by memory access operations from quickly conducting or radiating out of a memory, thereby trapping the heat within the memory. Increases of the memory's temperature caused by this trapped heat often effect the electrical characteristics of the memory device (e.g., cell voltages), which compromises the memory's reliability.